Structure and Mask Design for 3D RESURF Double-Gate DMOSFET

Abstract

A new 3D RESURF double-gate DMOSFET structure was proposed for simpler fabrication processoptimization by using junction isolation (JI) technique instead of using SOI for isolation. The 3D RESURFstructure is known to have higher breakdown voltage than the conventional 2D RESURF structure. Thishas been done by adding the alternative pattern of NMOS and PMOS in the horizontal direction. Inaddition, a process simulation has been done and masks have been designed for fabrication of real devicesin the future. The simulation results suggest optimized fabrication process conditions in order to obtainappropriate dopant distribution required for the realization of RESURF structure. A process simulation hasalso been done for a p+/n+ alternative pattern which is an important part of 3D RESURF structures. In thecase of using 50-keV ion implantation with dose of 5x1015 cm-2 followed by annealing at 550 °C for 30minutes, when the width of p+ and n+ layer is 5 microns, the alternative pattern is very clear. Several newideas have been introduced in the mask design, such as using a racetrack structure and field plate to preventpremature breakdown. The goal of the mask design is to further increase the breakdown voltage of this new3D RESURF double-gate DMOSFET structure.

Keywords : 3D RESURF / Double-gate DMOSFET / Process Simulation / Mask Design