Nair, R. K. R., Pothiraj, S., & Nagarajan, R. (2020). P2CTS-3D IC: An Efficient Placement Aware Partitioning and Clock Tree Synthesis in 3D-integrated Circuits. Applied Science and Engineering Progress, 13(4), 377–393. Retrieved from https://ph02.tci-thaijo.org/index.php/ijast/article/view/242308