Trimming Lithography: An Alternative Technology for Sub-Resolution and Sub-Wavelength Patterning

Main Article Content

Nithi Atthi
Areerat Sriklad
Wutthinan Jeamsaksiri
Charndet Hruanun
Amporn Poyai
Rardchawadee Silapunt

Abstract

Lithography is one of the key technologies for scaling down a size of integrated circuits thus increasing the performance of an electronic device. Currently, there are many lithographic techniques that are potentially  capable to produce a nanometer feature size but the continuing development for a commercial use is still limited by extremely high investment especially on exposure equipment and mask. This paper introduces an alternative patterning technique called Trimming lithography as one of the strong candidates for future lithography, for producing sub-resolution and subexposure wavelength features. The pattern size can be downscaled by carefully adjusting the trim distance that is much higher than an original design linewidth. It is shown that the photoresist (PR) feature size can be scaled down with the acceptable profile to approximately 0.18 m from the original 0.8 m mask pattern with the 0.5 m resolution of the exposure tool. However, the pattern density of the line/space pattern becomes lower than that of the typical lithography. Different pattern qualities between dense and isolated patterns are probably explained by a diffraction occurring during a transmission of light through the mask slit.

Article Details

How to Cite
Atthi, N., Sriklad, A., Jeamsaksiri, W., Hruanun, C., Poyai, A., & Silapunt, R. (2012). Trimming Lithography: An Alternative Technology for Sub-Resolution and Sub-Wavelength Patterning. ECTI Transactions on Electrical Engineering, Electronics, and Communications, 10(2), 198–207. https://doi.org/10.37936/ecti-eec.2012102.170419
Section
Signal Processing

References

[1] R.F. Pease and S.Y. Chou, “Lithography and other patterning techniques for future electronics," Proc. of the IEEE, vol. 96, no. 2, pp. 248–270, February 2008.

[2] ITRS Reports. (2011, July). ITRS 2010 Update. [Online]. Available: https://www.itrs.net/reports.html

[3] B.J. Lin, “Optical lithographyŮ present and future challenges," C. R. Physique, vol. 7, pp. 858Ű-874, 2006.

[4] K. Ronse, “Optical lithographyŮa historical perspective," C. R. Physique, vol. 7, pp. 844Ű-857, 2006.

[5] L. Guo, “Nanoimprint lithography: methods and material requirements," Adv. Mater, vol. 19, pp. 495– 513, 2007.

[6] R. S. Ghaida, G. Torres, and P. Gupta, “Single-Mask Double-Patterning Lithography," Proc. of SPIE, vol. 7488, pp. 74882J-1 74882J-11, 2009.

[7] C. A. Mack, Field guide to optical lithography, SPIE field guides, vol. FG06, John E. Greivenkamp publisher, Series Editor, 2006.

[8] B. Hwang, J. Han, M-C. Kimt, S. Jung, N. Lim, S. Jin, Y. Vim, D. Kwak, J. Park, J. Choi, and K. Kim, “Comparison of double patterning technologies in NAND flash memory with sub-30nm node," IEEE, ISBN 978-1-4244-4353Ű6, 2009.