Impact of Strain on Fully Depleted Strained Gate Stack Double Gate MOSFET: A Simulation Study

Article Sidebar

PDF
Published: Jun 6, 2015
DOI: https://doi.org/10.37936/ecti-eec.2015132.171029
Keywords:
Gate stack (GS) Strain Ge mole fraction (X) SCEs Analog performance

Main Article Content

K. P. Pradhan
Department of Electrical Engineering, National Institute of Technology (NIT)
S. K. Mohapatra
Department of Electrical Engineering, National Institute of Technology (NIT)
P. K Sahu
Department of Electrical Engineering, National Institute of Technology (NIT)
S. Parija
Department of Electrical Engineering, National Institute of Technology (NIT)

Abstract

The fusion of strain engineering and multigate technology is implemented to design an advanced MOSFET model i.e. Fully Depleted Strained Gate Stack Double Gate (FD-S-GS-DG) in nanoscale regime. Both DC and Analog performances of FD-S-GS-DG are analyzed by varying the Ge mole fraction (X). The sensitivity of crucial device parameters like threshold voltage (Vth), subthreshold swing (SS), on-current (Ion), off state leakage current (Ioff), on-off ratio (Ion/Ioff), transconductance (gm), output conductance (gd), early voltage (VEA), gain (AV), transconductance generation factor (TGF) towards X are successfully evaluated and presented. From the obtained results, by considering appropriate value of X, one can enhance the device performance by an immense aspect.

Article Details

How to Cite
Pradhan, K. P., Mohapatra, S. K., Sahu, P. K., & Parija, S. (2015). Impact of Strain on Fully Depleted Strained Gate Stack Double Gate MOSFET: A Simulation Study. ECTI Transactions on Electrical Engineering, Electronics, and Communications, 13(2), 54–57. https://doi.org/10.37936/ecti-eec.2015132.171029
Issue
Vol. 13 No. 2 (2015): Regular Issue
Section
Circuits and Systems

This journal provides immediate open access to its content on the principle that making research freely available to the public supports a greater global exchange of knowledge.

- Creative Commons Copyright License

The journal allows readers to download and share all published articles as long as they properly cite such articles; however, they cannot change them or use them commercially. This is classified as CC BY-NC-ND for the creative commons license. 

- Retention of Copyright and Publishing Rights

The journal allows the authors of the published articles to hold copyrights and publishing rights without restrictions.

References

[1] N. K. Jha, and D. Chen, Nanoelectronic Circuit Design. Springer Science & Business Media, 2010.

[2] G. E. Moore, and others, "Cramming more components onto integrated circuits," Proc. IEEE, vol. 86, no. 1, pp. 82-85, Jan. 1998.

[3] Y. L. Sung-Mo Kang, Cmos Digital Integrated Circuits. Tata McGraw-Hill Education, 2003, p. 655.

[4] "The International Technology Roadmap for Semiconductors," 2011.

[5] C. Hu, Modern Semiconductor Devices for Integrated Circuits. Prentice Hall, 2009.

[6] J. P. Colinge, "The new generation of SOI MOSFETs, " Rom. J. Inf. Sci. Technol., vol. 11, no. 1, pp. 3-15, Jan. 2008.

[7] M. Bruel, "Silicon on insulator material technology, " Electron. Lett., vol. 31, no. 14, pp. 1201-1202, Jul. 1995.

[8] T. A. Langdo, M. T. Currie, R. Hammond, A. J. Lochtefeld, and E. A. Fitzgerald, "Strainedsemiconductor-on-insulator device structures." Google Patents, 2006.

[9] S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, "Nanoscale SOI N-MOSFETs with different Gate Engineering having Biaxial Strained Channel - A Superlative Study," J. Electron Devices, vol. 15,
pp. 1261-1268, Sep. 2012.

[10] P. K. Sahu, K. P. Pradhan, S. K. Mohapatra, P. K. Sahu, K. P. Pradhan, and S. K. Mohapatra, "A Study on SCEs of FD-S-SOI MOSFET in Nanoscale," Univers. J. Electr. Electron. Eng., vol. 2, no. 1, pp. 37-43, Jan. 2014.

[11] C. S. Kim, S. J. Jo, S. W. Lee, W. J. Kim, H. K. Baik, S. J. Lee, D. K. Hwang, and S. Im, "Highk and low-k nanocomposite gate dielectrics for low voltage organic thin lm transistors," Appl. Phys. Lett., vol. 88, no. 24, p. 243515, Jun. 2007.

[12] K. P. Pradhan, S. K. Mohapatra, P. K. Sahu, and D. K. Behera, "Impact of high-k gate dielectricon analog and RF performance of nanoscale DGMOSFET," Microelectronics J., vol. 45, no. 2, pp. 144-151, Feb. 2014.

[13] P. K. Agarwal, K. P. Pradhan, S. K. Mohapatra, and P. K. Sahu, "Insulating layer parameters are still in reduction of kink," 2012 Nirma Univ. Int. Conf. Eng., 2012, pp. 1-4.

[14] J. P. Colinge, "The SOI MOSFET: From single gate to multigate," in FinFETs and Other Multi-Gate Transistors, Springer US, 2008, pp.1âAS48.

[15] S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, "Effect of channel and gate engineering on Double Gate (DG) MOSFET-A comparative study," in Emerging Electronics (ICEE), 2012 International Conference on, 2012, pp. 1-3.

[16] K. P. Pradhan, S. K. Mohapatra, P. K. Agarwal, P. K. Sahu, D. K. Behera, and J. Mishra, "Symmetric DG-MOSFET With Gate and Channel EngineeringâAr: A 2-D Simulation Study," Microelectron. Solid State Electron, vol. 2, no. 1, pp. 1-9, Feb. 2013.

[17] L. Jin, L. Hong-Xia, L. Bin, C. Lei, and Y. Bo, "Study on two-dimensional analytical models for symmetrical gate stack dual gate strained silicon MOSFETs," Chinese Phys. B, vol. 19, no. 10, pp. 107302, Oct. 2010.

[18] K. Kim and T. Won, "Quantum-mechanical modeling and simulation of a novel nano-scale FET: Center-channel (CC) double-gate (DG) MOSFET", J. Korean Phys. Soc., vol. 47, pp. S558-S563, Nov. 2005.

[19] L. Jin, L. Hongxia, Y. Bo, C. Lei, and L. Bin "A two-dimensional analytical model of fully depleted asymmetrical dual material gate doublegate strained-Si MOSFETs," J. Semicond., vol. 32, no. 4, pp. 44005, Apr. 2011.

[20] N. Sugiyamaa, T. Mizuno, S. Takagi, M. Koike, and A. Kurob, "Formation of strained-silicon layer on thin relaxed-SiGe/SiO2/Si structure using SIMOX technology," Thin Solid Films, 1995, vol. 369, pp. 199-202, 2000.

[21] http://www.synopsys.com/, "Sentaurus TCAD UserâAZs Manual," in Synopsys Sentaurus Device, pp. 191-403.

[22] J. Welser, J. L. Hoyt, and J. F. Gibbons, "Electron Mobility Enhancement in S trained-Si NType Metal-Oxide- Semiconductor Field-Effect Transistors," IEEE Electron Device Letters, vol. 15, no. 3, pp. 100-102, Mar. 1994.