An All-Digital PLL Proposal using Gain Control Technique

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Published: Jan 7, 2016
DOI: https://doi.org/10.37936/ecti-eec.2016141.171076
Keywords:
Discrete-time model Phase locked loop

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Vlademir J. S. Oliveira
Electrical Engineering, State University of Mato Grosso
Wagner C. Mariani
Computer Science, Federal Institute of Santa Catarina
Fábio V. Grigollo
Electrical Engineering, State University of Mato Grosso

Abstract

Time-to-digital converter (TDC) has been the main technique used in all-digital phase-locked loops (ADPLL). However, this approach has several design issues, and the solutions to resolve them always increase the complexity of the system. In this paper, an alternative method for handle the frequency error detection using a type II ADPLL architecture is presented. The proposed technique does not perform direct conversion from time to digital, but employs the discrete-time processing of compared signals from phase error detection. This architecture has the advantage of scalability and integration of all-digital techniques and has less complexity than conventional ADPLLs. The derivation of equations for the proposed architecture and its noise analysis is provided. The results are validated through system level simulations using macro-models of the devices. The result of the transient simulation shows the theoretical predictions about the trajectory of output frequency.

Article Details

How to Cite
Oliveira, V. J. S., Mariani, W. C., & Grigollo, F. V. (2016). An All-Digital PLL Proposal using Gain Control Technique. ECTI Transactions on Electrical Engineering, Electronics, and Communications, 14(1), 12–20. https://doi.org/10.37936/ecti-eec.2016141.171076
Issue
Vol. 14 No. 1 (2016): Regular Issue
Section
Circuits and Systems

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