Physical insight of junctionless transistor with simulation study of Strained channel
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Published:
Oct 12, 2016
Keywords:
Mole fraction JLCT ION −IOFF Electric field (E-Field) Sili on on Insulator (SOI)
Main Article Content
Abstract
The article inquest towards junctionless transistor exploiting channel engineering technique with (Si1-xGex). An accurate and deep understanding of the gated resister with demonstration of lower off-state current, improve on-state drain current and transconductance with its conventional counterpart using numerical simulation. The strain is to improve the electron mobility with high electric field and to reduce the scattering rate across the channel. SGOI-JLCT have a great potential for low power switching applications.
Article Details
How to Cite
Vandana, B., Patro, B. S., Das, J. K., & Mohapatra, S. K. (2016). Physical insight of junctionless transistor with simulation study of Strained channel. ECTI Transactions on Electrical Engineering, Electronics, and Communications, 15(1), 1–7. https://doi.org/10.37936/ecti-eec.2017151.171267
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Circuits and Systems
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References
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[26] A. Majumdar, C. Ouyang, S. J. Koester, and W.Haensch, "Effects of substrate orientation and channel stress on short-channel thin SOI MOSFETs," IEEE Trans. Electron Devices, vol. 57, no. 9, pp. 2067-2072, 2010.
[27] J. P. Colinge, C. W. Lee, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, A. Kranti, and R. Yu, "Junctionless transistors: physics and properties," inSemiconductor-On-Insulator Materials for
anoelectronics Applications, Springer, 2011, pp.187-200.
[28] R. T. Doria, M. A. Pavanello, R. D. Trevisoli, M. de Souza, C. W. Lee, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, and others, "Analog operation of junctionless transistors at ryogenic temperatures," in SOI Conference (SOI), 2010 IEEE International, 2010, pp. 1-2.
[2] K. Roy, S. Mukhopadhyay, and H. Mahmoodi Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," Proc. IEEE, vol. 91, no. 2, pp. 305-327, 2003.
[3] K. K. Young, "Short-channel effect in fully depleted SOI MOSFETs," IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 399-402, 1989.
[4] S. M. Sze, "Physics of Semiconductor Devices," Third edit. John Wiley and Sons Inc, 2009.
[5] J. E. Lilienfeld, "Method and apparatus for controlling electric currents," 1925.
[6] J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. OâNeill, A. Blake, M. White, A.-M. Kelleher, B. M Carthy, and R. Murphy, "Nanowire transistors without junctions," Nat. Nanotechnol., vol. 5, no. 3, pp. 225-229, 2010.
[7] A. Kranti, R. Yan, C. W. Lee, I. Ferain, R. Yu, N. D. Akhavan, P. Razavi, and J. P. Colinge, "Junctionless nanowire transistor (JNT): Properties and design guidelines," in Proc. ESS-DERC, 2010, pp. 357-360.
[8] S. Gundapaneni, S. Ganguly, and A. Kottantharayil, "Bulk planar junctionless transistor (BPJLT): An attractive device alternative for scaling," IEEE Electron device Lett., vol. 32, no. 3, pp. 261-263, 2011.
[9] S. Gundapaneni, M. Bajaj, R. K. Pandey, K. V. R. M. Murali, S. Ganguly, and A. Kottantharayil, "Effect of band-to-band tunneling on junctionless transistors," IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 1023âAS1029, 2012.
[10] S. Gundapaneni, "Investigation of Junction-Less Transistor (JLT) for CMOS Scaling," Citeseer, 2012.
[11] S. Gundapaneni, S. Ganguly, and A. Kottantharayil, "Enhanced electrostatic integrity of short-channel junctionless transistor with high-spacers," IEEE Electron Device Lett., vol. 32, no. 10, pp. 1325-1327, 2011.
[12] Z. Cheng, A. J. Pitera, M. L. Lee, J. Jung, J. L. Hoyt, D. A. Antoniadis, and E. A. Fitzgerald,c"Fully depleted strained-SOI n-and p-MOSFETs on bonded SGOI substrates and study of the SiGe/BOX interface," IEEE Electron Device Lett., vol. 25, no. 3, pp. 147-149, 2004.
[13] K. Usuda, T. Mizuno, T. Tezuka, N. Sugiyama, Y. Moriyama, S. Nakaharai, and S. Takagi, "Strain relaxation of strained-Si layers on SiGe-on-insulator (SGOI) structures after mesa isolation," Appl. Surf. Sci., vol. 224, no. 1, pp. 113-116, 2004.
[14] F. Mayer, C. Le Royer, J.-F. Damlenourt, K. Romanjek, F. Andrieu, C. Tabone, B. Previtali, and S. Deleonibus, "Impact of SOI, Si 1-x Ge x OI and GeOI substrates on CMOS compatible tunnel FET performacne," in 2008 IEEE International Electron Devices Meeting, 2008, pp. 1-5.
[15] T. Irisawa, T. Numata, E. Toyoda, N. Hirashita, T. Tezuka, N. Sugiyama, and S. Takagi, "Physical understanding of strain-induced modulationof gate oxide reliability in MOSFETs," IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3159-3166, 2008.
[16] S. K. Mohapatra, K. P. Pradhan, P. K. Sahu, and S. Parija, "Impact of Strain on Fully DepletedcStrained Gate Stack Double Gate MOSFET: A Simulation Study," ECTI Trans. Electr. Eng. Electron. Commun., vol. 13, no. 2, pp. 54-57, 2015.
[17] W. J. Zhu, T. Tamagawa, M. Gibson, T. Furukawa, and T. P. Ma, "Effect of Al inclusion in HfO 2 on the physical and electrical properties of the dielectrics," IEEE Electron Device Lett., vol. 23, no. 11, pp. 649-651, 2002.
[18] M. Wu, Y. I. Alivov, and H. Morko, "High- dielectrics and advanced channel concepts for Si MOSFET," J. Mater. Sci. Mater. Electron., vol. 19, no. 10, pp. 915-951, 2008.
[19] M. V Fischetti and S. E. Laux, "Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys," J. Appl. Phys., vol. 80, no. 4, pp. 2234-2252, 1996.
[20] Y. Sun, S. E. Thompson, and T. Nishida, "Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors," J. Appl. Phys., vol. 101, no. 10, p. 104503, 2007.
[21] T. Tezuka, N. Sugiyama, and S. Takagi, "Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction," Appl. Phys. Lett., vol. 79, no. 12, pp. 1798-1800, 2001.
[22] C. K. Maiti and G. A. Armstrong, Applications of silicon-germanium heterostructure devices. CRC Press, 2001.
[23] W. Shockley and W. T. Read Jr, "Statistics of the recombinations of holes and electrons," Phys. Rev., vol. 87, no. 5, p. 835, 1952.
[24] S. Saha, "MOSFET test structures for two-dimensional device simulation," Solid. State. Electron., vol. 38, no. 1, pp. 69âAS73, 1995.
[25] http://www.synopsys.com/, "Sentaurus TCADUserâs Manual," in Synopsys Sentaurus Device, Synopsys, 2012.
[26] A. Majumdar, C. Ouyang, S. J. Koester, and W.Haensch, "Effects of substrate orientation and channel stress on short-channel thin SOI MOSFETs," IEEE Trans. Electron Devices, vol. 57, no. 9, pp. 2067-2072, 2010.
[27] J. P. Colinge, C. W. Lee, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, A. Kranti, and R. Yu, "Junctionless transistors: physics and properties," inSemiconductor-On-Insulator Materials for
anoelectronics Applications, Springer, 2011, pp.187-200.
[28] R. T. Doria, M. A. Pavanello, R. D. Trevisoli, M. de Souza, C. W. Lee, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, and others, "Analog operation of junctionless transistors at ryogenic temperatures," in SOI Conference (SOI), 2010 IEEE International, 2010, pp. 1-2.