Cascode Current Mirror for a Variable Gain Stage in a 1.8 GHz Low Noise Amplifier (LNA)
Main Article Content
Abstract
A high frequency CMOS variable gain low noise amplifier (VGLNA) constructed based on an inductive source degenerated LNA and a cascode current mirror is proposed. The 'variable' concept is to prevent the unwanted saturation phenomenon due to large input signal. A cascode current mirror cell which consumes minimal voltage headroom without sacrificing the accuracy of the circuit is proposed in the circuit. With a 0.18 m CMOS technology, this technique is applied on a VGLNA operating at 1.8 GHz for GSM band application. The simulation results reveal that the maximum gain is 17.29 dB with gain tuning range of 9.56 dB. The noise ¯gure (NF) is less than 0.92 dB with the power consumption of 9.34 mW at power supply of 1.8 V. Comparison with several same operating frequency LNA circuits published show that this work demonstrated among the lowest NF and highest IIP3 with compromise on the gain.
Article Details
This journal provides immediate open access to its content on the principle that making research freely available to the public supports a greater global exchange of knowledge.
- Creative Commons Copyright License
The journal allows readers to download and share all published articles as long as they properly cite such articles; however, they cannot change them or use them commercially. This is classified as CC BY-NC-ND for the creative commons license.
- Retention of Copyright and Publishing Rights
The journal allows the authors of the published articles to hold copyrights and publishing rights without restrictions.
References
[2] R. Point, M. Mendes, W. Foley,"A Differential 2.4 GHz Switched-Gain CMOS LNA for 802.11b and Bluetooth," IEEE Radio and Wireless Conference 2002, RAWCON 2002, pp. 221-224, Aug. 2002.
[3] E. Sacchi, I. Bietti, F. Gatta, F. Svelto and R. Castello, "A 2 dB NF, fully differential, variable gain, 900 MHz CMOS LNA," Symp. On VLSI Circuits 2000, pp. 94{97, June 2000.
[4] K. L. Fong, "Dual-band High Linearity Variable Gain Low Noise Ampli¯ers for Wireless Applications," Digest of Technical Papers IEEE Solid-State Circuits Conference 1999, pp. 224-225, Feb 1999.
[5] T. H. Lee, The design of CMOS Radio Frequency Integrated Circuit, 2nd ed., Cambridge University Press, 1998.
[6] K. Ohsato and T. Yoshimasu, "Internally Matched, Ultralow DC Power Consumption CMOS Ampli¯er for L-Band Personal Communications," IEEE Microwave and Wireless Components Letters, Vol. 14, No. 5, pp. 204-206, May 2004.
[7] C. Zhang, D. Huang and D. Lou, "Optimization of Cascode CMOS Low Noise Amplifier using Inter-stage Matching Network," IEEE Conf. on Electron Devices and Solid-State Circuits, pp.465-468, Dec 2003.
[8] J.-N. Yang, et. al., "A 1.75 GHz Inductor-less CMOS Low Noise Amplifier with High-Q Active Inductor Load," Proc. of 44th IEEE 2001 Midwest Symp. on Circuits and Systems, Vol. 2, pp. 816-819, Aug 2001.
[9] A. Liscidini, et. al., "A 0.13 m CMOS Front-End, for DCS1800/UMTS/802.11b-g with Multiband Positive Feedback Low-Noise Amplifier," IEEE Journal of Solid-State Circuits, Vol. 41, No. 4, pp. 981-989, April 2006.
[10] H. Lee and S. Mohammadi, "A 3GHz Subthreshold CMOS Low Noise Ampli¯er," IEEE Radio Frequency Integrated Circuits Symp. 2006, pp.4, June 2006.
[11] D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., 1997.
[12] S-. K. Tang, C-. F. Chan, C-. S. Choy and K-. P. Pun, "CMOS RF LNA with high ESD immunity," Proc. IEEE Asia Pacific Conf. on Circuits and Systems, Vol. 1, pp. 321-324, Dec 2004.
[13] S. Park and W. Kim, "Design of a 1.8 GHz Low-noise Amplifier for RF Front-end in a 0.8 m CMOS technology," IEEE Trans. Consumer Electronics, Vol. 47, No. 1, pp. 10-15, Feb 2001.