RNS based Programmable Decimation Filter for Multi-Standard Wireless Transceivers
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Abstract
Current research on radio frequency transceivers focuses on multi-standard architectures to attain higher system capacities and data rates. Multiple communication standards are made adaptable by performing channel select filtering on chip at baseband in digital domain. The computationally intensive decimation filter in a sigma-delta analog-to-digital converter plays an important role in channel selection for multi-mode systems. As these architectures are targeted for portable applications, an area and power efficient recon¯gurable implementation is an
implicit requirement. To this end, a multi-stage, programmable decimation ¯lter based on residue number system (RNS) that is adaptable for WCDMA and WLAN standards is presented in this research. Multi-stage decimation filter implementation offers low computational complexity and power dissipation. The FIR filters of the multi-stage decimator operating in RNS domain offers high data rate because of the carry free operations on smaller residues in parallel channels. Further power saving is achieved by reconfiguring the hardware architecture, and powering down the unused blocks in each mode of operation. For increased programmability modulo multifiplication is performed by index addition utilizing the arithmetic benefits associated with Galois ¯eld. Finally, a performance comparison of the proposed RNS based decimation ¯lter with traditional binary implementation is done in terms of area, critical path delay and power dissipation.
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References
[2] S. Jagannathan, "Discrete-Time Adaptive Control of Feedback Linearizable Nonlinear Systems," IEEE Proceedings of the 35th Conference on Decision and Control, Kobe, Japan, pp.4747-4752, 1996
[3] C. J. Barrett, "Low-power decimation filter design for multi-standard transceiver applications", Master of Science in Electrical Engineering, University of California, Berkeley.
[4] A. Ghazel, L. Naviner and K. Grati. "Design of down-sampling processors for radio communications", Analog Integrated Circuits and Signal Processing, 36, Kluwer academic publishers, pp. 31-38, 2003.
[5] J. Luis Tecpanecatl, Ashok Kumar and M. A. Bayoumi, "Low complexity decimation filter for multistandard digital receivers", IEEE International Symposium on Circuits and Systems, (ISCAS 2005), Vol. 1, pp. 552-555, May 2005.
[6] S. D' Amico, M. De Matteis and A. Baschirotto, "A 6.4mW, 4.9nV/ n p Hz, 24dBm IIP3 VGA for a multi-standard (WLAN, UMTS, GSM and Bluetooth) receiver", 32nd European Solid-State Circuits Conference, pp. 82-85, September 2006.
[7] Ze Tao and S. Signell, "Multi-standard delta-sigma decimation filter design", IEEE Asia Pacific Conference on Circuits and Systems (APC-CAS 2006), Singapore, pp. 1212-1215, Dec.
2006.
[8] F. Sheikh and S. Masud, "E±cient sample rate conversion for multi-standard software defined radios", IEEE Int. Conf. on Acoustics, Speech and Signal Processing, HI, pp. II-329 - II-332, Apr. 2007.
[9] W. Li, J. Liu, J. Wang, C. Zhang and W. Guo, "An efficient digital IF down-converter for dual-mode WCDMA/EDGE receiver based on software radio", IEEE 6th CAS Symp. on Emerging Technologies: Mobile and Wireless Comm., China, pp. 713-716, May 31-June 2, 2004.
[10] M. Kim and S. Lee, "Design of dual-mode digital down converter forWCDMA and cdma2000", ETRI Journal, Vol.26, No.6, pp.555-559, Dec. 2004.
[11] J. Ramirez, A. Garcia, U. M-Baese and A. Lloris, "Fast RNS FPL-based communications receiver design and implementation", FPL 2002, LNCS 2438, pp. 472-481, Sept. 2002.
[12] Shahana T.K., R.K. James, B.R. Jose, K.P. Jacob and S.Sasi, "Performance analysis of FIR digital filter design: RNS versus traditional", 7th IEEE International Symp. on Communications and Information Technologies (ISCIT 2007), Australia, pp. 1-5, October 2007.
[13] Soderstrand M.A., Jenkins W.K., Jullien G.A., and Taylor F.J., Residue number system arithmetic: modern applications in digital signal processing, IEEE Press, New York, 1986.
[14] B. Parhami and C.Y. Huang, "Optimal look up schemes for VLSI implementation of input/output conversions and other residue number operations," in VLSI Signal Processing VII, J. Rabaey, P. M. Chau and Eldon, eds., IEEE Press, New York, 1994.
[15] D. Radhakrishnan, T. Srikanthan and J. Mathew, "Using the 2n property to implement an efficient general purpose residue-to-binary converter", Proceedings SCS '99, Iasi, Romania, July 1999, pp. 183-186.
[16] D. Radhakrishnan and Y. Yuan, "A fast RNS Galois field multiplier", IEEE International Symp. on Circuits and Systems, LA, USA, Vol.4, pp. 2909-2912, May 1990.
[17] D. Radhakrishnan, "Modulo multipliers using polynomial rings", IEE Proc. Circuits Devices syst., Vol. 145, No.6, December 1998.
[18] A.P. Preethy, D. Radhakrishnan and A.Omondi, "A high performance RNS multiply-accumulate unit", 11th Great Lakes symposium on VLSI, USA, pp.145-148, March 2001.
[19] G. L. Bernocchi, G.C. Cardarilli, A. D. Re, A. Nannarelli and M. Re, "Low-power adaptive filter based on RNS components", IEEE Int. Symp. on Circuits and Systems, pp. 3211-3214, May 2007.
[20] P. Gray and R. Meyer, "Future directions in silicon ICs for RF personal communications", Proc. of Custom Integrated Circuits Conference, pp. 83-90, May 1995.
[21] A.Xotta, A.Gerosa and A.Neviani, "A multimode analog-to-digital converter for GSM, UMTS and WLAN," IEEE Int. Symp. on Circuits and Systems, vol.3, pp. 2551-2554, May 2005.
[22] L. Zhang, V. Nadig and M. Ismail, "A high order multi-bit modulator for multi-standard wireless receiver", IEEE Int. Midwest Symp. on Circuits and Systems, pp. III-379-III-382, 2004.
[23] Z.Wang, G.A.Jullien and W.C.Miller, "An algorithm for multiplication modulo 2N¡1", Proc. 39th IEEE Midwest Symp. on Circuits Syst, pp. 1301-1304, 1996.