Exploring the Optimum Buffer Size of an Emerging Stream Cipher Engine

Abstract

One of crucial points for further improving ubiquitous network is to enhance temporary security without relying on permanent network infrastructure. Since a practical solution to provide such ubiquitous security is a safety aware, high-performed single chip processor, a multimedia stream cipher engine has been exploited. In order to keep security, usability, speed, and power consciousness, the stream cipher engine takes a compact multicore architecture. Each core implements a double cipher scheme that covers RAC (random addressing cryptography) and data sealing. The double cipher is microarchitecture based, software-transparent hardware cryptography that offers the protection of the whole data with negligible hardware cost and moderate performance overhead. Stream cipher engine chips have been developed by using 0.18-m standard cell CMOS technologies. Through the rough evaluation of those chips, it has emerged that streaming buffer size is crucial for prospective specifications. In order to achieve sophisticated design strategy, this paper evaluates in detail the buffer size  dependency of power dissipation, clock speed, running time, and throughput, focusing on the latest version of the stream cipher engine chip. From the tradeoff between these specificative factors, the guideline of optimum buffer size is made clear in view of safety and performance for ubiquitous computing.