Exploring of Third-Order Cascaded Multi-bit Delta- Sigma Modulator with Interstage Feedback Paths
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Abstract
The emergence of mixed-signal integrated circuit results in the tremendous increase in the numbers of high performance data converters with the trend toward high resolution and large bandwidth. Delta-Sigma modulator, employing oversampling technique, provides high output precision by shaping the in-band quantization noise to the out-of-band. This paper explores characteristics of Thirdorder cascaded multibit Delta-Sigma modulator with interstage feedback paths using behavioural simulation. Comparisons between mathematical models with behavioural models are demonstrated for theoretical analysis. Simulation models with various non-ideal sources of Delta-Sigma modulator are presented. A comparative analysis of
non-ideal effects including sampling jitter noise, integrator noise, integrator nonidealities, and capacitor mismatch on a cascaded architecture with interstage feedback paths of a Thirdorder multi-bit Delta-Sigma modulator are also discussed.
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