Exploring of Third-Order Cascaded Multi-bit Delta- Sigma Modulator with Interstage Feedback Paths

Sarayut Amornwongpeeti; Mongkol Ekpanyapong; Chumnarn Punyasai

doi:10.37936/ecti-eec.201191.172312

Authors

Sarayut Amornwongpeeti Department of Microelectronics and Embedded System, Asian Institute of Technology
Mongkol Ekpanyapong Department of Microelectronics and Embedded System, Asian Institute of Technology
Chumnarn Punyasai Thai Microelectronics Center (TMEC), National Electronics and Computer Technology Center (NECTEC)

DOI:

https://doi.org/10.37936/ecti-eec.201191.172312

Keywords:

Delta-Sigma Modulator, Non-idealities, Simulation Model, Interstage, Feedback Paths

Abstract

The emergence of mixed-signal integrated circuit results in the tremendous increase in the numbers of high performance data converters with the trend toward high resolution and large bandwidth. Delta-Sigma modulator, employing oversampling technique, provides high output precision by shaping the in-band quantization noise to the out-of-band. This paper explores characteristics of Thirdorder cascaded multibit Delta-Sigma modulator with interstage feedback paths using behavioural simulation. Comparisons between mathematical models with behavioural models are demonstrated for theoretical analysis. Simulation models with various non-ideal sources of Delta-Sigma modulator are presented. A comparative analysis of
non-ideal effects including sampling jitter noise, integrator noise, integrator nonidealities, and capacitor mismatch on a cascaded architecture with interstage feedback paths of a Thirdorder multi-bit Delta-Sigma modulator are also discussed.

References

[1] R. L. Carley, R. Schreier and G. C. Temes, "Delta- Sigma ADCs with multibit internal converters," Delta- Sigma Data Converters: Theory, Design, and Simulation, IEEE Press New York, NY, 1997.

[2] J. C. Candy, "An overview of basic concepts," Delta- Sigma Data Converters: Theory, Design, and Simulation, IEEE Press New York, NY, 1997.

[3] T. C. Leslie and B. Singh, "An improved sigmadelta modulator architecture," IEEE International Symposium on Circuits and Systems (ISCAS), Vol.1, pp.372-375, 1990.

[4] S. Lindfors and K. Halonen, "Two-step quantization in multibit ¢§ modulators," IEEE Transactions on Circuits and Systems II, Vol.48, pp.171-176, 2001.

[5] M. C. Ramesh and K. S. Chao, "Pipelined sigmadelta modulators with interstage scaling," 42nd Midwest Symposium on Circuits and Systems (MWSCAS), vol. 1, pp. 39-42, 1999.

[6] C. H. Su and K. S. Chao, "A fourth-order cascaded sigma-delta modulator with DAC error cancellation technique," The 2002 45th Midwest Symposium on Circuits and Systems (MWSCAS-2002), Vol.1, pp.132- 135, 2002.

[7] L. Fang and K. S. Chao, "A multi-bit sigmadelta modulator with interstage feedback," Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (ISCAS 98), Vol.1, pp.583-586, 1998.

[8] S. Brigati et al, "Modeling sigma-delta modulator non-idealities in Simulink," Proceedings of the 1999 IEEE International Symposium on Circuits and Systems (ISCAS 99), Vol.2, pp.384-387, 1999.

[9] A. Fornasari, P. Malcovati and F. Maloberti, "Improved modeling of sigma-delta modulator nonidealities in Simulink," IEEE International Symposium on Circuits and Systems (ISCAS2005), Vol.6, pp.5982-5985, 2005.

[10] H. Zare-Hoseini, I. Kale and O. Shoaei, "Modeling of switched-capacitor delta-sigma modulators in simulink," IEEE Transactions on Instrumentation and Measurement, Vol.54, pp.1646-1654, 2005.

[11] W. Koe and J. Zhang, "Understanding the effect of circuit non-idealities on sigma-delta modulator," Proceedings of the 2002 IEEE International Workshop on Behavioral Modeling and Simulation (BMAS 2002), pp.94-101, 2002.

[12] P. Malcovati et al., "Behavioral modeling of switched-capacitor sigma-delta modulators," IEEE Transactions on Circuits and Systems I, Vol.50, pp.352-364, 2003.

[13] Y. Matsuya et al., "A 16-bit oversampling A-to-D conversion technology using triple integration noise shaping," IEEE Journal of Solid-State Circuits, Vol. 22, pp.921-929, 1987.

[14] M. Rebeschini, "The design of cascaded ¢§ ADCs," Delta-Sigma Data Converters: Theory, Design, and Simulation, IEEE Press New York, NY, 1997.