Accurate Estimation of Power Consumption for Binary Comparator System using Back Tracking
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Abstract
This paper presents a binary comparator circuit design using minimum fan-in logic gates (NAND-NOR) to achieve a low power-delay product (PDP). A 2-bit binary comparator circuit is re-designed to minimize logic gate fan-in. Utilizing the concept of a 2-bit comparator, the general gate-level architecture of a comparator system is proposed for higher input operands. In this work, a backtracking model is proposed to estimate the worst-case performance in terms of delay and power for binary comparator circuits. It combines the advantages of the simulation-based method for power estimation and dynamic timing analysis (DTA) techniques for timing analysis. This work also extends to 20, 16, 14, 10, and 7-nm FinFET technology. The comparator circuits are simulated on the Pyxis Schematic tool using Mentor Graphics.
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