West First Turn Routing Algorithm with Backtracking Mechanism for on Chip Networks
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Abstract
In order to design high-performance and energy-efficient electronic systems, this research article is an attempt to investigate the usage of Network-on-Chip architectures as a possible substitute for conventional bus-based interconnects in the integrated circuits. This study primarily focuses on backtracking strategies for assessing the West First Turn routing protocol. Increasing the scalability and efficiency of Network on Chip based electronic systems by analyzing parameters like energy usage and resource utilization. This article presents a comparative study of XY routing, West First Turn routing, and Odd-Even Turn routing along with the West First Turn routing with backtracking mechanism for handling such issues including wormhole flow control in the Network on Chip architecture. Simulations results for the for a 3x3 mesh network coded in Verilog-HDL using Xilinx Vivado 2021.1 infers that West First Turn routing with backtracking mechanism is found better in terms of simplicity, adaptability, and resource utilization efficiency. This article will help researchers in proffering valuable insights and inferences for their research and development work as a contribution to the comprehension of associated challenges, potential solutions, and advancements for the selecting an appropriate routing mechanism in accordance with particular design specifications. The knowledge shared in this study not only advances Network on Chip technology but also offers useful recommendations for creating scalable and effective computing systems.
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