An Asynchronous C-ternary Combinational logic for Low-Voltage Applications
Main Article Content
Abstract
An asynchronous C-ternary combinational logic circuit employs based on a tripartite logic system, where the intermediate value ($V_{\mathrm{DD}}/2$) represents a spacer state. Spacer detector (SD) circuits are essential for identifying this spacer value. However, ultra-low supply voltages impose challenges on the reliable representation of the intermediate logic level. To overcome this limitation, this work proposes a low-voltage C-ternary combinational logic circuit that leverages the resistive-like characteristics of MOSFETs to generate the logical middle value. In addition, an optimized SD circuit is presented, which reduces transistor count and improves circuit efficiency. The proposed circuits were implemented and simulated using the 65 nm process at supply voltages of 0.5 V and 0.9 V in the Cadence Virtuoso analog design environment. The simulation results demonstrate the impact of temperature variations and analyze the propagation delay under both operating conditions.
Article Details
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
This journal provides immediate open access to its content on the principle that making research freely available to the public supports a greater global exchange of knowledge.
- Creative Commons Copyright License
The journal allows readers to download and share all published articles as long as they properly cite such articles; however, they cannot change them or use them commercially. This is classified as CC BY-NC-ND for the creative commons license.
- Retention of Copyright and Publishing Rights
The journal allows the authors of the published articles to hold copyrights and publishing rights without restrictions.
References
T. E. Williams, Self-timed rings and their application to division, PhD. Thesis, Stanford University, Stanford, CA, USA, 1992.
T. Felicijan and S. B. Furber, “An asynchronous ternary logic signaling system,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6, pp. 1114 –1119, Dec. 2003.
J.-M. Philippe, E. Kinvi-Boh, S. Pillement, and O. Sentieys, “An energy-efficient ternary interconnection link for asynchronous systems,” in Proceedings of 2006 IEEE International Symposium on Circuits and Systems, May 2006, p. 4 – 1014.
E.-J. Choi, K.-R. Cho, and J.-H. Lee, “New Data Encoding Method with a Multi-Value Logic for Low Power Asynchronous Circuit Design,” in 36th International Symposium on Multiple-Valued Logic (ISMVL’06), May 2006, pp. 4–4.
A. Doostaregan, M. H. Moaiyeri, K. Navi, and O. Hashemipour, “On the design of new lowpower CMOS standard ternary logic gates,” in 2010 15th CSI International Symposium on Computer Architecture and Digital Systems, Sep. 2010, pp. 115–120.
G. Thrishala and K. Ragini, “Design and Implementation of Ternary Logic Circuits for VLSI Applications,” International Journal of Innovative Technology and Exploring Engineering, vol. 9, no. 4, pp. 3117–3121, Feb. 2020.
G. Zhao, Z. Zeng, X. Wang, A.G. Qoutb, P. Coquet, E.G. Friedman, B.K. Tay, and M. Huang, “Efficient Ternary Logic Circuits Optimized by Ternary Arithmetic Algorithms,” IEEE Transactions on Emerging Topics in Computing, vol. 12, no. 3, pp. 826–839, Jul. 2024
J. Ko, K. Park, S. Yong, T. Jeong, T. H. Kim, and T. Song, “An Optimal Design Methodology of Ternary Logic in Iso-device Ternary CMOS,” in 2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL), May 2021, pp. 189–
J. Ko, J. Kim, T. Jeong, J. Jeong, and T. Song, “Exploration of Ternary Logic Using T-CMOS for Circuit-Level Design,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 9, pp. 3612–3624, Sep. 2023.
A. S. Vidhyadharan and S. Vidhyadharan, “A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM,” Microelectronics Journal, vol. 111, p.p. 105033, May 2021.
E. Abbasian, S. Sofimowloodi, and A. Sachdeva, “Highly-Efficient CNTFET-Based Unbalanced Ternary Logic Gates,” ECS Journal of Solid State Science and Technology, vol. 12, no. 3, p. 031007, Mar. 2023.
S. Kim, S.-Y. Lee, S. Park, K. R. Kim, and S. Kang, “A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 9, pp. 3138–3151, Sep. 2020.
C. K. Vudadha and M. Srinivas, “Design Methodolo-gies for Ternary Logic Circuits,” in 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), May 2018, pp. 192–197.
K. Chauhan, S. Mittra, R. Sinha, and D. Bansal, “Noise Margin analysis of Efficient CNTFETbased Standard Ternary Inverter,” in 2023 International
Conference for Advancement in Technology (ICONAT), Jan. 2023, pp. 1–7.
R. A. Jaber, A. M. Haidar, A. Kassem, and F. Zahoor, “Ternary Full Adder Designs Employing Unary Operators and Ternary Multiplexers,” icromachines,
vol. 14, no. 5, Art. no. 5, May 2023.
Z. T. Sandhie, F. U. Ahmed, and M. H. Chowdhury, “Design of Ternary Logic and Arithmetic Circuits Using GNRFET,” IEEE Open Journal of Nanotechnology,
vol. 1, pp. 77–87, 2020.
B. D. Madhuri and S. Sunithamani, “Design of ternary logic gates and circuits using GNRFETs,” IET Circuits, Devices & Systems, vol. 14, no. 7, pp.
–979, 2020.
Yang, H. Lee, J. H. Jeong, T. H. Kim, S.-H. Lee, and T. Song, “A Practical Implementation of the Ternary Logic Using Memristors and MOSFETs,” in 2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL), May 2021, pp. 183– 188.
X.-Y. Wang, C.T. Dong, P.F. Zhou, S.K. Nandi, S.K. Nath, R.G. Elliman, H.H.C. Iu, S.M. Kang, and J.K. Eshraghian, “Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 6, pp. 2423–2434, Jun. 2022.
G.-C. Lizeth, T. Asai, and M. Motomura, “Low power asynchronous digital pipeline based on mismatch-tolerant logic gates,” IEICE Electronics Express, vol. 11, no. 15, pp. 20140632–20140632, 2014.
Y. Shizuku, T. Hirose, N. Kuroki, M. Numa, and M. Okada, “Energy-efficient AES SubBytes transformation circuit using asynchronous circuits for ultra-low voltage operation,” IEICE Electron. Express, vol. 12, no. 4, pp. 20141157– 0141157, 2015.
A. Wheeldon, J. Morris, D. Sokolov, and A. Yakovlev, “Self-timed, minimum latency circuits for the internet of things,” Integration, vol. 69, pp. 138–146, Nov. 2019.
Z. Zhu, Y. Yu, X. Bai, S. Qiao, and Y. Hei, “Snake: An asynchronous pipeline for ultra-low-power applications,” IEICE Electron. Express, vol. 16, no. 12, pp. 20190293–20190293, 2019.
A. Wheeldon, A. Yakovlev, R. Shafik, and J. Morris, “Low-Latency Asynchronous Logic Design for Inference at the Edge,” in 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Feb. 2021, pp. 370–373.
Y. Nagata and M. Mukaidono, “Design of an asynchronous digital system with B-ternary logic,” in Proceedings 1997 27th International Symposium
on Multiple- Valued Logic, May 1997, pp. 265–271.
T. Bunnam and A. Thongtak, “An Approach for the Delay Simulation of D-Inverter in C-Ternary Logic Circuits,” in Proceedings of the 2008 International
Conference on Computer Design, CDES 2008, Las Vegas, Nevada, USA, July 14-17, 2008, H. R. Arabnia, Ed., CSREA Press, 2008, pp. 224–228.
P. Srikram and T. Bunnam, “A Design of Low Voltage Spacer Detector Circuits for Asynchronous Ternary Logic System,” in TENCON 2023 - 2023
IEEE Region 10 Conference (TENCON), Oct. 2023, pp. 460–463.
B. Razavi, Design of Analog CMOS Integrated Circuits, 1st ed. USA: McGraw-Hill, Inc., 2000.
N. H. E. Weste and D. M. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed., Boston, MA, USA: Addison-Wesley, 2010.
S. Kalra, “Effect of temperature dependence on performance of Digital CMOS circuit technologies,” in 2013 International conference on signal
processing and communication (ICSC), Dec. 2013, pp. 392–395.
