Evolution of CMOS Integrated Circuits: From MOSFET to FinFET

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Jirayut Mahattanakul

Abstract

This paper presents the developmental progress of CMOS integrated circuit fabrication from the early 1970’s till present time. In the first part of the paper, evolution of the structure and materials to produce MOSFET devices over the years will be summarized. And in the second part, the new kind of device namely FinFET, which is expected to make possible the continuation of the scaling down of CMOS IC in the future, will be discussed.

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Academic Article

References

G.E. Moore, “Cramming more components onto integrated circuits,” Electronics, vol. 38, No. 8, April 1974.

R.H. Dennard, F. H. Gaensslen, H-N Yu, V. L. Rideout, E. Bassous and A. R. Leblanc, “Design of ion-implant MOSFET with very small physical dimensions,” IEEE Journal of Solid-State Circuits, vol. 8, pp. 256-268, 1974.

F. Gaggin, T. Klein and L. Vadasz, “Insulated gate field effect transistor with silicon gates,” IEEE International Electron Devices Meeting (IDEM) Technical Digest, Washington D. C., 1968.

K. Jain., C. G. Wilson and B. J. Lin, “Ultrafast deep-UV lithography with excimer lasers”, IEEE Electron Device Letters, Vol. EDL-3, 53, 1982.

J. C. Hu, et al. Feasibility of Using W/TiN as Metal Gate for Conventional 0.13 Pm CMOS Technology and Beyond. ,” International Electron Devices Meeting (IEDM) Technical Digest, 1997.

K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappelani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, K. Zawadzki, “A 45nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging,” International Electron Devices Meeting (IEDM) Technical Digest, pp. 247-250, Dec. 2007.

Y. Sun, S. E. Thompson and T. Nishida, "Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors," Journal of Applied Physics, 2007.

X. Huang, W-C Lee, C Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y-K Choi, K. Asano, V. Subramanian, T-J King, J. Bokor and C. Hu, , "Sub 50-nm FinFET: PMOS" International Electron Devices Meeting (IEDM) Technical Digest, December 1999.

"Globalfoundries looks leapfrog fab rivals with new process". EE Times. Retrieved 2014-03-10.

J. Lien and Steve Shen,."TSMC likely to launch 16 nm FinFET+ process at year-end 2014, and "FinFET Turbo" later in 2015-16,” DIGITIMES. Retrieved 2014-03-31.

R. Merritt, ”FinFETs race toward silicon,” EE Times, Oct 2015., Retrieved 2015-10-3.

K. G. Orphanides, “IBM carbon nanotube breakthrough takes processor beyond silicon,” Wired, Oct 2015.

A. Mallik, J. Ryckaert, A. Mercha, D Verkest, K. Ronse, and A. Thean, "Maintaining Moore’s law: enabling cost-friendly dimensional scaling." SPIE Advanced Lithography. International Society for Optics and Photonics, April, 2015