A Back-to-Back Matching Network Implementation Technique for Accurate Characterization of Source/Load Impedance Seen by Power Transistor in RF Power Amplifier Design

Abstract

This paper presents a simple and more accurate measurement of matching network characteristics for an RF power amplifier, specifically its driving point impedances as seen by the power transistor, which are critical to its operational performances. The proposed technique relies on an implementation using the same matching network connected in a back-to-back configuration to avoid direct measurement on the matching network port that is connected to the power transistor, which has a relatively large pad size so as to connect with the gate and drain terminals of the power transistor package. This serves to mitigate an interconnect discontinuity between the matching layout and the 50-ohm transmission line layout to a network analyzer. The measured responses based on the back-to-back implementation is then employed to optimize the component values of the matching network schematic so as to fit the measurement with simulation, thereby enabling the implementation of the schematic to more accurately determine the driving point impedance. Validation of the technique is given via practical design and implementation of a 3.1-GHz GAN power amplifier.