Automated High-level Modeling of Power, Temperature and Timing Variation for Microprocessor

Main Article Content

Zheng Wang
Shazia Kanwal
Lai Wang
Anupam Chattopadhyay


The continued scaling of semiconductor technologies leads to diverse challenges such as power and temperature, which also forces reliability as another design metric of prime concern. There exists strong need to link reliability with physical metrics in a high-level architecture design environment, where estimation of reliability impacts can be performed in the early design stage. In this paper, we propose a joint modeling and simulation framework for power, thermal and timing variation, which is integrated into a commercial high-level processor design environment. A custom timing variation model is provided for estimation of dynamic timing variation, which is demonstrated using one nanoscale thermal effect known as Inverted Temperature Dependence. The complete modeling flow is automated for customized processor model with arbitrary architectural hierarchy, which assists designer to perform architectural and application-level design space exploration with power, thermal and reliability impacts.

Article Details

How to Cite
Wang, Z., Kanwal, S., Wang, L., & Chattopadhyay, A. (2017). Automated High-level Modeling of Power, Temperature and Timing Variation for Microprocessor. Applied Science and Engineering Progress, 10(3), 163–175. Retrieved from
Research Articles


[1] V. Tiwari, S. Malik, and A. Wolfe, “Power analysis of embedded software: A first step towards software power minimization,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, no. 4, pp. 437–445, 1994.

[2] V. Tiwari, S. Malik, A. Wolfe, and M. Tien-Chien Lee, “Instruction level power analysis and optimization of software,” The Journal of VLSI Signal Processing, vol. 13, no. 2, pp. 223–238, 1996.

[3] D. Brooks, V. Tiwari, and M. Martonosi, “Watch: A framework for architectural-level power analysis and optimizations,” in Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201), 2000, pp. 83–94.

[4] S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi, “Mcpat: An integrated power, area, and timing modeling framework for multicore and manycore architectures,” in Proceedings 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2009, pp. 469–480.

[5] H. Blume, D. Becker, M. Botteck, J. Brakensiek, and T. Noll, “Hybrid functional and instruction level power modeling for embedded processors,” in Proceedings Embedded Computer Systems: Architectures, Modeling, and Simulation, 2006, pp. 216–226.

[6] Y. Park, S. Pasricha, F. Kurdahi, and N. Dutt, “A multi-granularity power modeling methodology for embedded processors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, pp. 668–681, 2011.

[7] M. A. Alam and S. Mahapatra, “A comprehensive model of PMOS NBTI degradation,” Microelectronics Reliability, vol. 45, no. 1, pp. 71–81, 2005.

[8] K. Kanda, K. Nose, H. Kawaguchi, and T. Sakurai, “Design impact of positive temperature dependence on drain current in sub-1-v cmos vlsis,” IEEE Journal of Solid-State Circuits, vol. 36, no. 10, pp. 1559–1564, 2001.

[9] K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, “Temperatureaware microarchitecture,” ACM SIGARCH Computer Architecture News, vol. 31, no. 2, pp. 2–13, 2003.

[10] W. Huang, S. Ghosh, K. Sankaranarayanan, K. Skadron, and M. R. Stan, “Hotspot: Thermal modeling for CMOS VLSI systems,” IEEE Transactions on Componenst Packaging and Manufacturing Technology, pp. 200–205, 2005.

[11] J. Donald and M. Martonosi, “Techniques for multicore thermal management: Classification and new exploration,” in Proceedings 33rd International Symposium on Computer Architecture (ISCA’06), vol. 34, 2006, pp. 78–88.

[12] L. Pohl, “Multithreading and strassens algorithms in sunred field solver,” in Proceedings 14th International Workshop on Thermal Inveatigation of ICs and Systems, 2008, pp. 137–141.

[13] A. Sridhar, A. Vincenzi, D. Atienza, and T. Brunschwiler, “3d-ice: A compact thermal model for early-stage design of liquid-cooled ics,” IEEE Transactions on Computers, vol. 63, no. 10, pp. 2576–2589, 2014.

[14] V. Szekely, A. Poppe, A. Pahi, A. Csendes, G. Hajas, and M. Rencz, “Electro-thermal and logi-thermal simulation of vlsi designs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 5, no. 3, pp. 258–269, 1997.

[15] A. Timár and M. Rencz, “High resolution temperature dependent timing model in digital standard cell designs,” Journal of Low Power Electronics, vol. 9, no. 4, pp. 414–420, 2013.

[16] A. Timár and M. Rencz, “Temperature dependent timing in standard cell designs,” Microelectronics Journal, vol. 45, no. 5, pp. 521–529, 2014.

[17] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “Cacti 6.0: A tool to model large caches,” HP Laboratories, pp. 22–31, 2009.

[18] M.-y. Hsieh, A. Rodrigues, R. Riesen, K. Thompson, and W. Song, “A framework for architecturelevel power, area, and thermal simulation and its application to network-on-chip design exploration,” ACM SIGMETRICS Performance Evaluation Review, vol. 38, no. 4, pp. 63–68, 2011.

[19] F. Terraneo, D. Zoni, and W. Fornaciari, “An accurate simulation frame-work for thermal explorations and optimizations,” in Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2015, pp. 5:1–5:6.

[20] G. Nagy and A. Poppe, “A novel simulation environment enabling multilevel power estimation of digital systems,” in Proceedings 17th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), 2011, pp. 1–4.

[21] Z. Wang, L. Wang, H. Xie, and A. Chattopadhyay, “Power modeling and estimation during adl-driven embedded processor design,” in Proceedings 2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC), 2013, pp. 97–102.

[22] Synopsys. (2017). Processor Designer. Synopsys Inc., CA. [Online]. Available:

[23] A. Chattopadhyay, H. Meyr, and R. Leupers, LISA: A Uniform ADL for Embedded Processor Modelling, Implementation and Software Toolsuite Generation, Morgan Kaufmann, 2008, pp. 95–130.

[24] HotSpot. (2015, Jun.). HotSpot 6.0.[Online]. Available:

[25] Z. Wang, C. Chen, and A. Chattopadhyay, “Fast reliability exploration for embedded processors via high-level fault injection,” in Proceedings International Symposium on Quality Electronic Design (ISQED), 2013, pp. 265–272.

[26] D. Kammler, J. Guan, G. Ascheid, R. Leupers, and H. Meyr, “A fast and flexible Platform for fault injection and evaluation in verilogbased simulations,” in Proceedings 3rd IEEE International Conference on Secure Software Integration and Reliability Improvement (SSIRI), 2009, pp. 309–314.

[27] J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. Springer Science & Business Media, 2009.

[28] A. Krstic,Y.-M. Jiang, and K.-T. Cheng, “Pattern generation for delay testing and dynamic timing analysis considering power-supply noise effects,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 3, pp. 416–425, 2001.

[29] T. Sakurai and A. R. Newton, “Alpha-power law mosfet model and its applications to cmos inverter delay and other formulas,” IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp. 584– 594, 1990.

[30] A. Sassone, A. Calimera, A. Macii, E. Macii, M. Poncino, R. Goldman, V. Melikyan, E. Babayan, and S. Rinaudo, “Investigating the effects of inverted temperature dependence (ITD) on clock distribution networks,” in Proceedings 2012 Design, Automation & Test in Europe Conference &Exhibition (DATE), 2012, pp. 165–166.

[31] W. Zhao and Y. Cao, “New generation of predictive technology model for sub-45 nm early design exploration,” IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 2816–2823, 2006.