Energy-Efficient 16-bit RCA and CSLA Design Using MTCMOS with Sleep Transistor Optimization
DOI:
https://doi.org/10.37936/ecti-eec.2027251.265385Keywords:
Ripple Carry Adder (RCA), Carry Select Adder (CSLA), Low Power VLSI design, MTCMOS (Multi-Threshold CMOS), Power GatingAbstract
Leakage power has become a major concern in deep submicron CMOS technologies, particularly in arithmetic circuits where performance and energy efficiency must be balanced. This work presents the transistor-level design and analysis of 16-bit Ripple Carry Adder (RCA) and Carry Select Adder (CSLA) architectures implemented in 90 nm CMOS technology. A variable block CSLA structure is employed to reduce carry propagation delay, and MTCMOS-based power gating is integrated using a high-threshold PMOS header sleep transistor to suppress leakage power. Simulation results obtained using Cadence Virtuoso demonstrate that the CSLA achieves lower propagation delay compared to RCA, while MTCMOS integration significantly reduces standby leakage power from the micro-watt range to the pico-watt range. In addition, a parametric study of sleep transistor sizing is performed to identify the optimal trade-off between leakage reduction and performance degradation. The results indicate that combining architectural optimization with power-gating techniques enables efficient low-power adder design, making the proposed approach suitable for energy-constrained VLSI applications.
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