Delayed Log-Domain Reservoir Computing for Ultra-Low-Resource FPGAs

Abstract

This paper presents a complete time-multiplexed reservoir for ultra-low-resource, DSP-free FPGAs, combining a 128-word state delay, 100 virtual nodes, deterministic signed masks, approximate log-domain multiplication, interpolated activation, and a quantized streaming readout. Delay states and 16-bit weights share one 4-kbit memory, while generated states are accumulated directly into the output. The architecture, reservoir hyperparameters, and training procedure are frozen before five independent NARMA-10 confirmation runs; a separate readout is fitted for each sequence. The implementation obtains normalized root-mean-square error $0.3544\pm0.0359$, compared with $0.5160\pm0.0345$ for an 11-tap linear baseline and $0.3833\pm0.0347$ for an exact-multiplier reservoir using the same hyperparameters selected for the approximate design. Python and RTL outputs agree exactly. On a DSP-free iCE40 HX8K target, approximation removes 19.85\% of LUT4 cells and 18.65\% of placed logic cells while retaining one block RAM. The routed design operates at 23.569~MHz and produces one result every 601 cycles. These results establish an end-to-end accuracy--area operating point for streaming reservoir inference on a DSP-free FPGA target.