High Priority Arbitration for Less Burst Data Transactions for Improved Average Waiting Time of Multi-Processor Cores
Article Sidebar
Main Article Content
Abstract
The multi-processor cores in SoC which have high burst data transactions can play a critical role while accessing the shared resources such as the off-chip memory. These processor cores can starve other processor cores that have less burst data transactions while accessing the same shared resources. The starving issue of other processor cores leads to degrade the entire system performance of the SoC. However, the arbiter architecture in the SoC design plays the best solution to manage different processor core requests and granting one of them to access the shared resources according to different scheduling algorithms. In this paper, we have designed AXI interconnect, which includes arbiter architecture to connect four processor cores represented by the AXI masters and the off-chip memory represented by the salve. Each processor core (AXI Master) uses the AXI4 interface protocol to improve the system performance and the arbiter based on the static fixed-priority algorithm to improve the average waiting time for all the processor cores. The SoC design architecture is modeled in System Verilog HDL; simulation and synthesis are done by using the Vivado tool and FPGA ZYNQ-7 ZC702 Evaluation Board (xc7z020clg484-1).
Article Details
References
[2] R. Khanam, H. Sharma, and S. Gaur “Design a less latency Arbiter for on chip communication architecture,” in International Conference on Computing, Communication and Automation, 2015.
[3] M. N. Akhtar and O. Sidek, “An intelligent arbiter for maximum CPU utilization, fair bandwidth allocation and less latency: Survey,” in IEEE 8th International Colloquium on Signal Processing and its Applications, 2012.
[4] M. N. Akhtar and J. M. Saleh, “Parallel adaptive arbiter for improved CPU utilization and fair bandwidth allocation,” in International Conference on Circuits, Systems, Signal Processing, Communications and Computers, 2015.
[5] Arm Limited, “AXI Reference Guide, UG1037 (v4.0),” 2017. [Online]. Available: http://www. amba.com
[6] S. S. Math and R. B. Manjula “Design of AMBA AXI4 protocol for system-on-chip communication,” International Journal of Communication Network and Security, vol. 1, pp. 38–42, 2012.
[7] A. Noami, A. Alahdal, B. P. Kumar, P. Chandrasekhar, and N. Safi, “High speed data transactions for memory controller based on AXI4 interface protocol SoC,” in The IEEE 1st International Conference on Advances in Electrical, Computing, Communications and Sustainable Technologies, 2021.
[8] J. Gupta and N. Goel, “Efficient bus arbitration protocol for SoC design,” in International Conference on Smart Technologies and Management for Computing, Communication, Controls, Energy and Materials, 2015, pp. 396– 400.
[9] A. Shrivastava and S. K. Sharma, “Various arbitration algorithm for on-chip (AMBA) shared bus multiprocessor SoC,” in IEEE Students' Conference on Electrical, Electronics and Computer Science, 2016.
[10] R. Khanam and Z. Ahmad, “Finite state machine based arbiter for on chip communication architecture,” in International Conference on Computing, Communication and Automation, 2016.
[11] A. Ingle and P. Srividya, “Design and simulation of multi master AHB lite bus interconnect,” in Proceedings of the IEEE International Conference on Computing Methodologies and Communication, 2017.
[12] B. M. Shankaranarayana and V. V. Malode, “Design and implementation of power efficient arbiter module for AMBA AHB protocol,” International Journal of Advanced Research in Computer Engineering & Technology, vol. 3, pp. 2141–2145, 2014.
[13] B. Tiwari and N. Goel, “Multi-master bus interface design using efficient lottery bus arbiter,” in IEEE Annual India Conference, 2016.
[14] A. Noami, B. P. Kumar, and P. Chandrasekhar “Design and implementation of a united multicore memory controller using AXI4-lite interface protocol,” International Journal on Emerging Technologies, vol. 11, no. 3, pp. 468–475, 2020.
[15] A. Noami, B. P. Kumar, and P. Chandrasekhar, “High performance AXI4 interface protocol for multi-core memory controller on SoC,” in the Springer 4th International Conference on Data Engineering and Communication Technology, 2020.
[16] S. V. Vijayalakshmi, A. Apsara, K. Preetha, and S. Cammillus “Memory arbitration in DDR3,” International Journal of Recent Technology and Engineering, vol. 8, pp. 3344–3347, 2020.